This invention generally relates to power reduction in a memory bus interface.
Computer systems use memory devices to store data that is associated with various operations of the system. Collectively, these devices may form the system memory for the computer system. To store data in and retrieve data from the system memory, the computer system typically includes a memory controller that is coupled to the system memory via a memory bus. The signals that propagate over the memory bus depend on the type of memory devices that form the system memory.
For example, one type of memory device is a synchronous dynamic random access memory (SDRAM), a device in which data signals are communicated to and from the SDRAM device over the memory bus in synchronization with positively sloped, or positive going, edges (for example) of a clock signal. This basic type of SDRAM is known as a single data rate (SDR) SDRAM, as the data is clocked once every cycle of the clock signal. In contrast to the single data rate SDRAM, in the operation of a double data rate (DDR) SDRAM, data is clocked both on the positive going and negative going edges of a clock signal (called a data strobe signal), thereby giving rise to the phrase “double data rate.”
The data strobe signal, called the “DQS data strobe signal,” is furnished either by the system memory or the memory controller, depending on whether a read or write operation is occurring over the memory bus. A SDR SDRAM device does not use the DQS data strobe signal. In a write operation with a DDR SDRAM device, the memory controller furnishes bits of data to the memory bus by controlling the logic levels of data bit lines (called the “DQ data bit lines”) of the memory bus. In the write operation, the memory controller furnishes the DQS data strobe signal such that each edge of the DQS data strobe signal is synchronized to a time at which a particular set of data bits (furnished by the memory controller via the DQ data bit lines) is valid on the memory bus. In this manner, the memory controller may offset the phase of the DQS data strobe signal relative to the data bit signals so that the edges of the DQS data strobe signal occur when the particular set of data bits are valid. For example, the DQS signal may be ninety degrees out of phase with the signals present on the DQ data bit lines. Thus, for example, the memory controller furnishes a first set of bits to the memory bus. When these bits are valid, the DQS data strobe signal has a positive going edge. The memory controller furnishes the next set of bits to the memory bus. When these bits are valid, the DQS data strobe signal has a negative going edge, etc.
For a read operation, the above-described role is reversed between the DDR SDRAM device and the memory controller. In this manner, for a read operation, the DDR SDRAM device furnishes both the DQS data strobe and controls the signals that appear on the DQ data bit lines.
When neither a write nor a read operation is occurring over the memory bus, DQ data bit lines as well as the DQS data strobe lines remain at a termination level, a level that may be, for example, between the logic zero and logic one voltage levels. Thus, a potential difficulty with this arrangement is that an input sense amplifier of the memory controller (for example), which receives and amplifies the signal from one of the DQ data bit lines, may use a reference voltage near the termination level. It is this reference voltage that the sense amplifier uses to distinguish a logic one voltage (i.e., a voltage greater than the reference voltage) from a logic zero signal (i.e., a voltage less than the reference voltage). Thus, noise on a particular DQ data signal line may inadvertently appear as a logic one or logic zero voltage to the associated sense amplifier when neither a write nor a read operation is actually occurring over the memory bus. This event may cause inadvertent operation of the sense amplifier and thus, excess power may be dissipated by the amplifier and possibly other circuitry of the memory controller due to this operation.
Thus, there is a continuing need for an arrangement and/or technique to address one or more of the problems that are stated above.